In metal oxide semiconductor (MOS) electrically erasable, programmable read only memory (EEPROM) transistors, electrons tunnel through very thin silicon dioxide (SiO.sub.2, "oxide") layers to be stored on or removed from a storage location, known as a floating gate. The electric charge, or lack of electric charge, stored on the floating gate in turn determines whether a transistor controlled by the floating gate can be turned on or off, thereby functioning as a programmable memory cell. More precisely, charge on the floating gate shifts the threshold voltage at which the transistor conducts. At a low threshold voltage, representing an unprogrammed state, designated a digital one, the transistor conducts when selected by a reference voltage applied to a sense gate, a gate above the floating gate. At a higher threshold voltage, representing a programmed state, designated a digital zero, the transistor does not conduct when selected under the same conditions.
The area of the thin dielectric layer through which electron tunneling occurs is limited to small generally rectangular dimensions and the thinness of the layer is carefully controlled. For this reason the rectangular area is termed a "window." Oxide windows having a thickness of between 70 angsttoms to 200 angstroms and an area of one half to several square microns are typical. U.S. Pat. No. 4,590,503 to Harari describes formation of a thin tunnel oxide region.
A silicon substrate that has been doped with ions is located below the floating gate, separated by a dielectric layer. The thin tunnel oxide window dielectric separating the floating gate layer from the substrate provides the region for electrons to tunnel between the substrate and the floating gate.
The area and the thickness of the tunnel oxide window are two of the most important factors in the performance of EEPROM memory cells. For any significant tunneling to occur, the difference in voltage between the floating gate and the substrate must exceed a threshold voltage, the threshold voltage being generally related to the both the area and thickness of the tunneling window. The sense gate affects the floating gate through capacitive coupling, and a similar capacitive coupling exists between the floating gate and the substrate. Since the voltage difference between the sense gate and the substrate is the sum of the voltage difference between the floating gate and the substrate and the voltage difference between the floating gate and the sense gate, a lower threshold voltage allows a lower voltage to be applied between the sense gate and the substrate for charging and discharging. Alternatively, a lower threshold voltage allows the memory cell to be charged or discharged more quickly, entailing a higher tunneling current.
A smaller tunneling window area is advantageous in at least three ways. First, as explained above, a smaller window allows the memory cell to be read or written either with a lower applied voltage or more quickly, or both. Each of these possibilities offers user benefits, such as an increase in programming speed or a reduction in energy consumption. Second, a smaller window area allows the cell and the whole transistor circuit to be made smaller, and the resultant scaling down in size of large arrays of such circuits has the benefits of packing more information capabilities in a smaller package. Thus a smaller tunneling window offers the promise of better performance and more memory in a smaller package. Third, a smaller window area allows the possibility of lowering write and erase voltages.
The tunnel oxide window is typically produced during the fabrication of the EEPROM by the deposition of layers and etching by conventional photoresist techniques. As the area of tunnel oxide windows approaches and even becomes smaller than the resolution of the photoresist patterning and etching, conventional photoresist techniques present a limit to the size that these windows can be accurately made.
It is therefore an object of the present invention to provide a method for forming submicron area tunnel oxide windows that are not restricted by the limits inherent in conventional photoresist and etching processes, or by the limits of lithography.